Department of Electronics Engineering
NIT Uttarakhand, Srinagar Garhwal
System-on-Chip (SoC) is the important key component for the integrated smart system design. All kinds of SoC are designed using different IP cores or functional block in silicon platform, which are inter-linked together by on-chip bus communication architecture (OCBCA) to ensure optimum performance. Fairness to access and waiting time to access are very important characteristic for an arbiter. It’s very difficult to analyze the performance of any arbiter accurately. Here we proposed an efficient methodology for testing and verification of on-chip bus arbiter in FPGA environment. The primary objective is to determine path delay and fairness characteristics of arbiter components for the On-chip bus of SoC by software Vivado-2013.4 environment and verified in the hardware Zynq (xc7z020) device of zed board environment.
On-chip bus of SoC;
Rajesh Saha, “On-Chip Bus Arbiter Testing and Verification in FPGA,” International Journal of Advanced Engineering and Management, Vol. 2, No. 8, pp. 196-199, 2017.
- S Roy, R Saha, and C T Bhunia, “On Efficient Minimization Techniques of Logical Constituents and Sequential Data Transmission for Digital IC,” Indian journal of science technology, vol. 9, no. 9, pp. 1-9, 2016.
- B Cordan, “An efficient bus architecture for system-on-a-chip design,” in 12th Custom Integrated Circuits Conference, , USA, 1999, pp. 623-626.
- R Saha, V Nandi, S Roy, and C T Bhunia, “Design and verifications of efficient arbiter of SoC’s on-chip bus,” in Proceeding of IEEE 3rd International Conference on Electronics and Communication Systems, India, 2016, pp. 989-992.
- Abdulsalam A Yayah, Yahaya Coulibaly, Abdul Samad Ismail, and George Rouskas, “Hybrid offset‐time and burst assembly algorithm (H‐OTBA) for delay sensitive applications over optical burst switching networks,” International Journal of Communication System, pp. 1-11, 2014.
- K Lahiri, A Raghunathan, and G Lakshminarayana, “LOTTERYBUS: new communication architecture for high-performance system-on-chip designs,” in Proceedings of 38th Design and Automation Conference, USA, 2001, pp. 15-20.
- Y S Cho, E J Choi, and K R Cho, “Modeling and analysis of the system bus latency on the SoC platform,” in Proceedings of International Workshop SLIP, Germany, 2006, pp. 67-74.
- Josep Torrellas, Tucker Andrew, and Anoop Gupta, “Evaluating the performance of cache-affinity scheduling in shared-memory multiprocessors,” Journal of Parallel and Distributed Computing, pp. 139-151, 1995.
- D Flynn, “AMBA: Enabling reusable on-chip designs,” IEEE Micro, vol. 17, no. 4, pp. 20-27, 1997.
- A Goel and R L William, “Formal verification of an IBM Core Connect processor local bus arbiter core,” in Proceedings of ACM 37th Annual Design Automation, USA, 2000, pp. 196-200.
- Xilinx. (2016) ISE Synthesis and Verification Design Guide. [Online]. http://www.xilinx.com.
- A Joao, “Bottleneck identification and acceleration in multithreaded applications (Doctoral dissertation).,” 2014.
- K Padmanabham, Prabhakar Kanugo, M Chandrashekar, and K. Nagabhushan Raju, “MIL-STD-1553 bus protocol algorithms implementation on fpga to realise system-on-chip (SOC),” International Journal of Advancements in Research & Technology, vol. 5, no. 5, pp. 1-8, 2016.