Home » On-Chip Bus Arbiter Testing and Verification in FPGA

On-Chip Bus Arbiter Testing and Verification in FPGA

Rajesh Saha

Project Engineer,
Department of Electronics Engineering
NIT Uttarakhand, Srinagar Garhwal


System-on-Chip (SoC) is the important key component for the integrated smart system design. All kinds of SoC are designed using different IP cores or functional block in silicon platform, which are inter-linked together by on-chip bus communication architecture (OCBCA) to ensure optimum performance. Fairness to access and waiting time to access are very important characteristic for an arbiter. It’s very difficult to analyze the performance of any arbiter accurately. Here we proposed an efficient methodology for testing and verification of on-chip bus arbiter in FPGA environment. The primary objective is to determine path delay and fairness characteristics of arbiter components for the On-chip bus of SoC by software Vivado-2013.4 environment and verified in the hardware Zynq (xc7z020) device of zed board environment.


Arbiter Mechanisms;
On-chip bus of SoC;

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Cited as

Rajesh Saha, “On-Chip Bus Arbiter Testing and Verification in FPGA,” International Journal of Advanced Engineering and Management, Vol.  2, No. 8, pp. 196-199, 2017.

DOI: https://doi.org/10.24999/IJOAEM/02080045


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