Home » Performances Analysis of High-Speed Low-Power 1-bit Full Adder

Performances Analysis of High-Speed Low-Power 1-bit Full Adder

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Kratikatiyar

kratikatiyar@gmail.com

Trinity College of Engineering, Bhopal, India

Praveen Kumar

praveenkumar8398@gmail.com

Trinity College of Engineering, Bhopal, India

Abstract

Analysis of a hybrid 1-bit full adder is discussed here. The adders are implemented and analysis to reduce the power dissipation and output voltage degradation. The simulation result of the full adder was performed using different technology with special stress on the design methodology and analysis. The Hybrid logic design the characteristics of altered logic or design styles, enhance overall performance. The delay introduced due to propagation is further minimized by transistor size also discussed in this paper. We also discussed their various performance parameters such as delay, power, and layout area etc.

Keywords

Delay approximation;

Hybrid full-adder;

Low-power full-adder;

Multiplexer based full adder design;

Power Delay Product.

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Cited as

Kratikatiyar and Praveen Kumar, “Performances Analysis of High-Speed Low-Power 1-bit Full Adder,” International Journal of Advanced Engineering and Management, Vol. 2, No. 5, pp. 106-108,  2017.                                      

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