Dept. of ECE, Scope college of Engineering, Bhopal, India
Multipliers are the most essential block of any processor. Multiplication is one of the important operations in digital signal processors. The processing speed of a ALU is depends on its logic algorithm and complexity of hardware circuitry delay. Basically delay is depending on number of bits increases. For efficient processors, delay should minimum; to minimize delay optimized hardware architecture for process is required. Vedic Multipliers are able to deal with the above credential of minimum hardware architecture. In this review a comprehensive analysis of binary multiplication algorithm and Vedic multiplication algorithm has presented.
Vedic multiplier, Vedic multiplier, Highspeed multiplier, binary multiplication algorithm.
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