Home » An Efficient Technique For Switching Functions Simplification

An Efficient Technique For Switching Functions Simplification


Sahadev Roy

Dept. of ECE, NIT Arunachal Pradesh, Yupia, 791112, India



In this paper, we propose a new approach for switching function simplification using octal coded minterms. This novel method of two-level minimization techniques effectively reduces the number of steps in comparison with other existing methods. A chart for octal based minimization for manual minimization process is also proposed herein. Proposed minimization method factorized minterms in a group of three input variables which are represented in octal code. These groups of minterms further paired with adjacent minterms. For easy detection, an octal chart also proposed here. The proposed method effectively reduces the complexity of multiple input minimization process. The results, which are verified by comparison with available experimental data, indicated that the minimal product of some was achieved with minimal effort.


Algorithm for Boolean function minimization;
Combinational logic,
Octal coded minterms;
Multiple inputs logic circuit minimization;
Switching circuit simplification;
Sum-of-Products (SOP);
Weighted sum.

pdf-1Download PDF

Cited as

Sahadev Roy, “An Efficient Technique For Switching Functions Simplification,” International Journal of Advanced Engineering and Management, Vol. 2, No. 1, pp. 21-28, 2017. https://ijoaem.org/00201-9

DOI: https://doi.org/10.24999/IJOAEM/02010009


  1. S. Roy and C.T. Bhunia,”On Synthesis of Combinational Logic Circuits,” International Journal of Computer Applications, vol. 127, no.1, pp. 21-26, 2015. DOI:10.5120/ijca2015906311
  2. J.H. Anderson, Q. Wang and C. Ravishankar, “Raising FPGA Logic Density Through Synthesis-Inspired Architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 3, pp. 537-550, 2012. DOI:10.1109/TVLSI.2010.2102781
  3. K. Kim, S. Shin and S.M. Kang, “Field Programmable Stateful Logic Array,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 12, pp. 1800-1813, 2011. DOI: 10.1109/TCAD.2011.2165067
  4. A. Mishchenko, R. Brayton, H.R. Jiang, and S. Jang, “Scalable Don’t-Care-Based Logic Optimization and Resynthesis,” ACM Transactions on Reconfigurable Technology and Systems, vol. 4, no. 4, 34, 2011. DOI: 10.1145/2068716.2068720
  5. P. Fiser, J. Hlavicka and H. Kubatova,”FC-Min: A Fast Multi-Output Boolean Minimizer,” Proceedings Euromicro Symposium on Digital System Design, IEEE, 2003, pp. 451-454. DOI: 10.1109/DSD.2003.1231982
  6. G. Borowik, T. Luba, and D. Zydek, “Features Reduction Using Logic Minimization Techniques,” International Journal of Electronics and Telecommunications, vol. 58, no. 1, 71-76, 2012. DOI: 10.2478/v10177-012-0010-x
  7. C.H. Chuang, C.L. Lin, Y.C. Chang, T. Jennawasin, and P.K. Chen, “Design of Synthetic Biological Logic Circuits Based on Evolutionary Algorithm,” IET Systems Biology, vol. 7, no. 4, pp. 89-105, 2013. DOI: 10.1049/iet-syb.2012.004
  8. R. Kumar, S. Roy and C.T. Bhunia, “Study of Threshold Gate and CMOS Logic Style Based Full Adder Circuits,” Proc. IEEE, 3rd Int. Conference on Electronics and Communication Systems (ICECS), IEEE, 2016, pp. 173-179.
  9. N. Song, and M.A. Perkowski, “Minimization of Exclusive Sum-of-Products Expressions for Multiple-Valued Input, Incompletely Specified Functions,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 4, pp. 385-395, 1996. DOI:10.1109/ISMVL.1993.289569
  10. R. Serrell, “Elements of Boolean Algebra for the Study of Information-Handling Systems,” Proc. of the IRE, vol. 41, no. 10, pp. 1366-1380, 1953. DOI:10.1109/JRPROC.1953.274313
  11. G. Nelson and D.C. Oppen, “Simplification by Cooperating Decision Procedures,” ACM Transactions on Programming Languages and Systems, vol. 1, no. 2, pp. 245-257, 1979. DOI: 10.1145/357073.357079
  12. S. Roy and C.T. Bhunia, “Constraints Analysis for Minimization of Multiple Inputs Logic Programming,” Proc. of International Conference on Signal and Speech Processing (ICSSP-14), Elsevier, 2014, pp. 61-64.
  13. S. Roy, S. Saha and C.T. Bhunia, “Multiple Inputs Combinational Logic Minimization by Minterms Set,” Proc. of the 1st Int. Conference on Recent Cognizance in Wireless Communication & Image Processing (ICRCWIP-2015), Springer, 2015, Ch. 15.
  14. V.T. Rhyne, P.S. Noe, M.H. McKinney and U.W. Pooch, “A New Technique for the Fast Minimization of Switching Functions,” IEEE Transactions on Computers, vol. 100, no. 8, pp. 757-764, 1977. DOI:10.1109/TC.1977.1674913
  15. M. Karnaugh, “The Map Method for Synthesis of Combinational Logic Circuits,” Transactions. AIEE, vol. 72, no. 5, pp. 593–599, 1953.
  16. S. Roy and C.T. Bhunia, “Simplification of Switching Functions Using Hex-Minterms,” International Journal of Applied Engineering Research, vol.10 no. 24, pp. 45619-45624, 2015.
  17. S. Roy, “Breakup Algorithm for Switching Circuit Simplifications,” International Journal of Advanced Engineering and Management, vol. 1, no. 1, pp.1-11, 2016.


%d bloggers like this: